Look at the 3nm process and how the gate pitch is 48nm and the metal pitch is 24nm. The names of the processes stopped having to do with the size of the transistors over a decade ago. It is stupid.
That is ridiculous. Does 3nm mean anything or it is purely marketing?
Every process name is basically a marketing a gimmick. You could sort of use the previous names as a ratio to get a general idea of uplift but that isn't really accurate either. To further confuse things Intel's naming scheme had bigger nm values but is a similar size to lower numbered names from TSMC.
Quantum tunneling has been an ongoing issue. Basically, they are using different design of transistors, different semiconductor material at the gate, and accepting that it is a reality and adding more error checks/corrections.
What's the threshold for quantum tunneling to be an issue? Cuz at such small scales, particles can...teleport through stuff.
It's important to note that 1.6nm is just a marketing naming scheme and has nothing to do with the actual size of the transistors.
https://en.m.wikipedia.org/wiki/3_nm_process
Look at the 3nm process and how the gate pitch is 48nm and the metal pitch is 24nm. The names of the processes stopped having to do with the size of the transistors over a decade ago. It is stupid.
That is ridiculous. Does 3nm mean anything or it is purely marketing?
Every process name is basically a marketing a gimmick. You could sort of use the previous names as a ratio to get a general idea of uplift but that isn't really accurate either. To further confuse things Intel's naming scheme had bigger nm values but is a similar size to lower numbered names from TSMC.
Quantum tunneling has been an ongoing issue. Basically, they are using different design of transistors, different semiconductor material at the gate, and accepting that it is a reality and adding more error checks/corrections.