Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows
cross-posted from: https://discuss.tchncs.de/post/2554454
The digital RAKs provide Arm Neoverse V2 designers with several key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, delivering better PPA and improving designer productivity. Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster design closure. The RAKs also include a smart hierarchy flow that delivers optimal turnaround times on large, high-performance CPUs. The Tempus ECO technology offers signoff-accurate final design closure based on path-based analysis. Finally, the RAKs incorporate the GigaOpt activity-aware power optimization engine to significantly reduce dynamic power consumption.
I know its an ad, but it's kind of interesting.
Switched from a long line of synopsys shops to a cadence shop, the design maturity is refreshing.
I do not want to see ads in my feed too but I found this interesting, also semiconductor tech is very industry-driven, so most news can be interpreted as an ad. Why do you think Cadence has more design maturity? Cadence is usually preferred or analog and mixed signal, but for RTL design-verification part whatever I need and have in Cadence, I find it in Synopsys as well.
My experience with synopsys has been mixed, and often brutal, lot of unfinished IP, errata to work around, the repurpose IP for a different application and there are hidden restrictions.
Otoh, it's generally cheap as hell, and the sim/emu platforms are great.
Mostly the IP seems half-thought out, even the stuff that's been around for years.
Brought up maybe 3 different generations of the pcie IP, never worked without a fight. DDR3/4/5 was the same.
They screwed up i2c, and UARTS! Not in high speed sync modes, just rs423. I don't even understand how that's possible.
Shouldn't rant, they had good moments too, it's just, their fae/tmes earn their pay.